I’m a PhD student in Computer Science at Georgia Tech. I’m currently working with Prof. Hyesoon Kim in the HPArch Lab at Georgia Tech. My main area of interest is architectural security and computer architecture in general.


I’m interested in working at the intersection of computer architecture and hardware security, specifically in the area of side-channel attacks and defenses as well as memory safety. My recent work involves mitigating timing based side-channel attacks on the interconnect using a randomization based system-level approach. This paper is currently under submission at a conference awaiting reviews. I am currently also looking into GPU accelerated RowHammer attacks and their defenses, as well as potential defenses for PACMAN-style speculative execution attacks.


Feb'23I will be joining AMD Research as Research Intern for the summer of 2023
Oct'22Serving as submission chair for ISCA 2023
Oct'22Gave a short presentation at NOCS'22 about our work NOICER: A system level approach to mitigating timing side channel attacks on the interconnect
Apr'22Received DAC Young Fellow '22 award. Comes with a travel grant + DAC conference registration worth $1000. Invited to attend IEEE Design Automation Conference and present a poster about my research (Georgia Tech News)
Feb'22Accepted to the PhD program at Georgia Tech. Will be continuing on as a MS/PhD student
Jan'22Will be joining Qualcomm as an intern during Summer '22. Also received an offer from Apple
Nov'21Serving on the Artifact Evaluation Committee for HPCA 2022
Aug'21Started grad school at Georgia Tech. Working with Prof. Hyesoon Kim in the area of memory safety
Dec'20Our paper based on my work on RGO+Ni2O3 nanocompisite for heavy metal sensing applications at IIT Kharagpur has been published in IEEE Transactions on Electron Devices
Apr'20I have been accepted into the MS in Computer Science Program for Fall'20 at Georgia Tech (Update: I have deferred my admission to Fall'21 because of the COVID-19 pandemic)
Dec'19I started my new job at ARM as a CPU Verification Engineer. I will be working on with RIS (Random Instruction Sequence) tools to stress and test the latest ARM IP's
Mar'19Travelling to Intel's office in Hillsboro, Oregon for SoC Power On activities
Jul'18Joined Intel as a System Validation Engineer. I'll be working on Thunderbolt(TM) technology at the Post-Si level